View MCP6V06_8427783.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2008 microchip technology inc. ds22093b-page 1 MCP6V06/7/8 features high dc precision: -v os drift: 50 nv/c (maximum) -v os : 3 v (maximum) -a ol : 125 db (minimum) - psrr: 125 db (minimum) - cmrr: 120 db (minimum) -e ni : 1.7 v p-p (typical), f = 0.1 hz to 10 hz -e ni : 0.54 vp-p (typical), f = 0.01 hz to 1 hz low power and supply voltages: -i q : 300 a/amplifier (typical) - wide supply voltage range: 1.8v to 5.5v easy to use: - rail-to-rail input/output - gain bandwidth product: 1.3 mhz (typical) - unity gain stable - available in single and dual - single with chip select (cs ): mcp6v08 extended temperature range: -40c to +125c typical applications portable instrumentation sensor conditioning temperature measurement dc offset correction medical instrumentation design aids spice macro models filterlab ? software mindi? circuit designer & simulator microchip advanced part selector (maps) analog demonstration and evaluation boards application notes related parts mcp6v01/2/3: spread clock, lower offset description the microchip technology inc. MCP6V06/7/8 family of operational amplifiers has input offset voltage correction for very low offset and offset drift. these devices have a wide gain bandwidth product (1.3 mhz, typical) and strongly reject switching noise. they are unity gain stable, have no 1/f noise, and have good psrr and cmrr. these products operate with a single supply voltage as low as 1.8v, while drawing 300 a/amplifier (typical) of quiescent current. the microchip technology inc. MCP6V06/7/8 op amps are offered in single (MCP6V06), single with chip select (cs ) (mcp6v08), and dual (mcp6v07). they are designed in an advanced cmos process. package types (top view) v in + v in C v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc v ina + v ina C v ss 1 2 3 4 8 7 6 5 v outa v dd v outb v inb C v inb + MCP6V06 soic mcp6v07 soic v in + v in C v ss v dd v out 1 2 3 4 8 7 6 5 nc cs nc mcp6v08 soic MCP6V06 2x3 tdfn * v in + v in C v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc * includes exposed thermal pad (ep); see ta b l e 3 - 1 . ep 9 mcp6v07 4x4 dfn * v ina + v ina C v ss v outb v inb C 1 2 3 4 8 7 6 5 v inb + v dd v outa ep 9 mcp6v08 2x3 tdfn * v in + v in C v ss v dd v out 1 2 3 4 8 7 6 5 nc cs nc ep 9 300 a, auto-zeroed op amps downloaded from: http:///
MCP6V06/7/8 ds22093b-page 2 ? 2008 microchip technology inc. typical application circuit offset voltage correction for power driver MCP6V06 c 2 r 2 r 1 r 3 mcp6xxx v dd /2 3k v in v out r 2 downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 3 MCP6V06/7/8 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd Cv ss .......................................................................6.5v current at input pins ....................................................2 ma analog inputs (v in + and v in C) ?? ... v ss C 1.0v to v dd +1.0v all other inputs and outputs ............ v ss C 0.3v to v dd +0.3v difference input voltage ...................................... |v dd Cv ss | output short circuit current ................................ continuous current at output and supply pins ............................30 ma storage temperature ...................................-65c to +150c max. junction temperature ........................................ +150c esd protection on all pins (hbm, mm) ................ 4 kv, 300v ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rati ng only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximu m rating conditions for extended periods may affect device reliability. ?? see section 4.2.1 rail-to-rail inputs . 1.2 specifications table 1-1: dc electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2, r l = 20 k to v l , and cs = gnd (refer to figure 1-5 and figure 1-6 ). parameters sym min typ max units conditions input offset input offset voltage v os -3 +3 v t a = +25c (note 1) input offset voltage drift with temperature (linear temp. co.) tc 1 -50 +50 nv/c t a = -40 to +125c (note 1) input offset voltage quadratic temp. co. tc 2 0.15 nv/c 2 t a = -40 to +125c power supply rejection psrr 125 142 db (note 1) input bias current and impedance input bias current i b + 6p a input bias current across temperature i b + 1 4 0 p at a = +85c i b +1500 +5000 pa t a = +125c input offset current i os - 8 5 p a input offset current across temperature i os - 8 5 p at a = +85c i os -1000 -190 1000 pa t a = +125c common mode input impedance z cm 1 0 13 ||6 ||pf differential input impedance z diff 1 0 13 ||6 || pf common mode common-mode input voltage range v cmr v ss ? 0.20 v dd +0.20 v (note 2) common-mode rejection cmrr 120 136 db v dd = 1.8v, v cm = -0.2v to 2.0v ( note 1, note 2) cmrr 130 147 db v dd = 5.5v, v cm = -0.2v to 5.7v ( note 1, note 2) open-loop gain dc open-loop gain (large signal) a ol 125 147 db v dd =1.8v, v out = 0.2v to 1.6v (note 1) a ol 135 158 db v dd =5.5v, v out = 0.2v to 5.3v (note 1) note 1: set by design and characterization. d ue to thermal junction and other effects in the production environment, these parts can only be screened in production (except tc 1 ; see appendix b: offset related test screens ). 2: figure 2-18 shows how v cmr changed across temperature for t he first three production lots. downloaded from: http:///
MCP6V06/7/8 ds22093b-page 4 ? 2008 microchip technology inc. output maximum output voltage swing v ol , v oh v ss +15 v dd ? 15 mv g = +2, 0.5v input overdrive output short circuit current i sc 7m a v dd =1.8v i sc 2 2 m av dd =5.5v power supply supply voltage v dd 1.8 5.5 v quiescent current per amplifier i q 200 300 400 a i o = 0 por trip voltage v por 1.15 1.65 v table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2, r l = 20 k to v l , and cs = gnd (refer to figure 1-5 and figure 1-6 ). parameters sym min typ max units conditions note 1: set by design and characterization. d ue to thermal junction and other effects in the production environment, these parts can only be screened in production (except tc 1 ; see appendix b: offset related test screens ). 2: figure 2-18 shows how v cmr changed across temperature for t he first three production lots. table 1-2: ac electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2, r l = 20 k to v l , c l = 60 pf, and cs = gnd (refer to figure 1-5 and figure 1-6 ). parameters sym min typ max units conditions amplifier ac response gain bandwidth product gbwp 1.3 mhz slew rate sr 0.5 v/s phase margin pm 65 g = +1 amplifier noise response input noise voltage e ni 0.54 v p-p f = 0.01 hz to 1 hz e ni 1.7 v p-p f = 0.1 hz to 10 hz input noise voltage density e ni 8 2 n v / hz f < 2.5 khz e ni 5 2 n v / hz f = 100 khz input noise current density i ni 0.6 fa/ hz amplifier distortion (note 1) intermodulation distortion (ac) imd 32 v pk v cm tone = 50 mv pk at 1 khz, g n = 1, v dd = 1.8v imd 25 v pk v cm tone = 50 mv pk at 1 khz, g n = 1, v dd = 5.5v amplifier step response start up time t str 500 s v os within 50 v of its final value offset correction settling time t stl 300 s g = +1, v in step of 2v, v os within 50 v of its final value output overdrive recovery time t odr 100 s g = -100, 0.5v input overdrive to v dd /2, v in 50% point to v out 90% point (note 2) note 1: these parameters were characterized using the circuit in figure 1-7 . figure 2-37 and figure 2-38 show both an imd tone at dc and a residual tone at1 khz; all other imd and clock tones are spread by the randomization circuitry. 2: t odr includes some uncertainty due to clock edge timing. downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 5 MCP6V06/7/8 table 1-3: digital electrical specifications table 1-4: temperature specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2, r l = 20 k to v l , c l = 60 pf, and cs = gnd (refer to figure 1-5 and figure 1-6 ). parameters sym min typ max units conditions cs pull-down resistor (mcp6v08) cs pull-down resistor r pd 35m cs low specifications (mcp6v08) cs logic threshold, low v il v ss 0 . 3 v dd v cs input current, low i csl 5p a cs = v ss cs high specifications (mcp6v08) cs logic threshold, high v ih 0.7v dd v dd v cs input current, high i csh v dd /r pd p a cs = v dd cs input high, gnd current per amplifier i ss - 0 . 7 a cs = v dd , v dd = 1.8v i ss - 2 . 3 a cs = v dd , v dd = 5.5v amplifier output leakage, cs high i o_leak 2 0p a cs = v dd cs dynamic specifications (mcp6v08) cs low to amplifier output on turn-on time t on 11 100 s cs low = v ss +0.3 v, g = +1 v/v, v out = 0.9 v dd /2 cs high to amplifier output high-z t off 1 0 s cs high = v dd C 0.3 v, g = +1 v/v, v out = 0.1 v dd /2 internal hysteresis v hyst 0 . 2 5v electrical characteristics: unless otherwise indicated, al l limits are specified for: v dd = +1.8v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 +125 c operating temperature range t a -40 +125 c (note 1) storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8l-2x3 tdfn ja 4 1 c / w thermal resistance, 8l-4x4 dfn ja 4 4 c / w (note 2) thermal resistance, 8l-soic ja 150 c/w note 1: operation must not cause t j to exceed maximum junction tem perature specification (150c). 2: measured on a standard jc51-7, four layer prin ted circuit board with ground plane and vias. downloaded from: http:///
MCP6V06/7/8 ds22093b-page 6 ? 2008 microchip technology inc. 1.3 timing diagrams figure 1-1: amplifier start up. figure 1-2: offset correction settling time. figure 1-3: output overdrive recovery. figure 1-4: chip select (mcp6v08). 1.4 test circuits the circuits used for the dc and ac tests are shown in figure 1-5 and figure 1-6 . lay the bypass capacitors out as discussed in section 4.3.8 supply bypassing and filtering . r n is equal to the parallel combination of r f and r g to minimize bias current effects. figure 1-5: ac and dc test circuit for most non-inverting gain conditions. figure 1-6: ac and dc test circuit for most inverting gain conditions. the circuit in figure 1-7 tests the op amp inputs dynamic behavior (i.e., imd, t str , t stl and t odr ). the potentiometer balances th e resistor network (v out should equal v ref at dc). the op amps common mode input voltage is v cm =v in /2. the error at the input (v err ) appears at v out with a noise gain of 10 v/v. figure 1-7: test circuit for dynamic input behavior. v dd v os v os +50v v os C50v t str 0v 1.8v to 5.5v 1.8v v in v os v os +50v v os +50v t stl v in v out v dd v ss t odr t odr v dd /2 v il high-z t on v ih cs t off v out -2 a high-z i ss -2 a 300 a 1a i dd 1a 300 a v dd /5 m i cs v dd /5 m 5pa (typical) (typical) (typical) (typical) (typical) (typical) (typical) (typical) (typical) v dd mcp6v0x r g r f r n v out v in v dd /3 1f c l r l v l 100 nf r iso v dd mcp6v0x r g r f r n v out v dd /3 v in 1f c l r l v l 100 nf r iso v dd mcp6v0x v out 1f c l r l v l 100 nf r iso 20.0 k 24.9 20.0 k 50 v in v ref 0.1% 0.1% 25 turn 20.0 k 20.0 k 0.1% 0.1% 2.49 k 2.49 k downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 7 MCP6V06/7/8 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. 2.1 dc input precision figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input offset voltage quadratic temp co. figure 2-4: input offset voltage vs. power supply voltage with v cm =v cmr_l . figure 2-5: input offset voltage vs. power supply voltage with v cm =v cmr_h . figure 2-6: input offset voltage vs. output voltage. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes on ly. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 input offset voltage (v) percentage of occurrences 80 samples t a = +25c v dd = 1.8v and 5.5v soldered on pcb 0% 5% 10% 15% 20% 25% -50 -40 -30 -20 -10 0 1020 30 40 50 input offset voltage drift; tc 1 (nv/c) percentage of occurrences 80 samples v dd = 1.8v and 5.5v soldered on pcb 0% 5% 10% 15% 20% 25% 30% -0.4 -0.2 0.0 0.2 0.4 input offset voltage's quadratic temp co; tc 2 (nv/c 2 ) percentage of occurrences 80 samples v dd = 1.8v and 5.5v soldered on pcb -4 -3 -2 -1 0 1 2 3 4 0.00.51.01.52.02.53.03.54.04.55.05.56.06.5 power supply voltage (v) input offset voltage (v) +125c+85c +25c -40c v cm = v cmr_l representative part -4 -3 -2 -1 0 1 2 3 4 0.00.51.01.52.02.53.03.54.04.55.05.56.06.5 power supply voltage (v) input offset voltage (v) +125c+85c +25c -40c v cm = v cmr_h representative part -4 -3 -2 -1 0 1 2 3 4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) input offset voltage (v) v dd = 1.8v v dd = 5.5v representative part downloaded from: http:///
MCP6V06/7/8 ds22093b-page 8 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. figure 2-7: input offset voltage vs. common mode voltage with v dd =1.8v. figure 2-8: input offset voltage vs. common mode voltage with v dd =5.5v. figure 2-9: cmrr. figure 2-10: psrr. figure 2-11: dc open-loop gain. figure 2-12: cmrr and psrr vs. ambient temperature. -4 -3 -2 -1 0 1 2 3 4 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 input common mode voltage (v) input offset voltage (v) v dd = 1.8v representative part -40c +25c+85c +125c -4 -3 -2 -1 0 1 2 3 4 -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input common mode voltage (v) input offset voltage (v) v dd = 5.5v representative part +125c +85c +25c -40c 0% 5% 10% 15% 20% 25% 30% 35% -0.4 -0.3 -0.2 -0.2 -0.1 0.00.1 0.2 0.2 0.3 0.4 1/cmrr (v/v) percentage of occurrences 39 samples t a = +25c soldered on pcb v dd = 1.8v v dd = 5.5v 0% 2% 4% 6% 8% 10% 12% 14% -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 1/psrr (v/v) percentage of occurrences 40 samples t a = +25c soldered on pcb 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 1/a ol (v/v) percentage of occurrences 40 samples t a = +25c soldered on pcb v dd = 1.8v v dd = 5.5v 120 125 130 135 140 145 150 155 160 -50 -25 0 25 50 75 100 125 ambient temperature (c) cmrr, psrr (db) psrr cmrr v dd = 5.5v v dd = 1.8v downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 9 MCP6V06/7/8 note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. figure 2-13: dc open-loop gain vs. ambient temperature. figure 2-14: input bias and offset currents vs. common mode input voltage with t a =+85c. figure 2-15: input bias and offset currents vs. common mode input voltage with t a = +125c. figure 2-16: input bias and offset currents vs. ambient temperature with v dd = +5.5v. figure 2-17: input bias current vs. input voltage (below v ss ). 120 125 130 135 140 145 150 155 160 -50 -25 0 25 50 75 100 125 ambient temperature (c) dc open-loop gain (db) v dd = 5.5v v dd = 1.8v -150 -100 -50 0 50 100 150 200 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input bias, offset currents (pa) i b t a = +85c v dd = 5.5v i os -400 -200 0 200 400 600 800 1000 1200 1400 1600 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input bias, offset currents (pa) i b t a = +125c v dd = 5.5v i os 1 10 100 1,000 10,000 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) input bias, offset currents (pa) v dd = 5.5v -i os i b 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c+25c -40c 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p downloaded from: http:///
MCP6V06/7/8 ds22093b-page 10 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. 2.2 other dc voltages and currents figure 2-18: input common mode voltage headroom (range) vs. ambient temperature. figure 2-19: output voltage headroom vs. output current. figure 2-20: output voltage headroom vs. ambient temperature. figure 2-21: output short circuit current vs. power supply voltage. figure 2-22: supply current vs. power supply voltage. figure 2-23: power on reset trip voltage. -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 -50 -25 0 25 50 75 100 125 ambient temperature (c) input common mode voltage headroom (v) lower (v cmr C v ss ) upper ( v dd C v cmr ) 3 lots 10 100 1000 0.1 1 10 output current magnitude (ma) output voltage headroom (mv) v dd C v oh v dd = 5.5v v ol C v ss v dd = 1.8 v 0 1 2 3 4 5 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 ambient temperature (c) output headroom (mv) v dd C v oh v dd = 5.5v v ol C v ss v dd = 1.8v r l = 20 k ? -40 -30 -20 -10 0 10 20 30 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) output short circuit current (ma) -40c +25c +85c +125c +125c +85c +25c -40c 0 50 100 150 200 250 300 350 400 450 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) supply current (a) +125c +85c +25c -40c 0% 5% 10% 15% 20% 25% 30% 1.11.2 1.3 1.4 1.5 1.6 1.7 por trip voltage (v) percentage of occurrences 93 samples 3 lots t a = +25c downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 11 MCP6V06/7/8 note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. figure 2-24: power on reset voltage vs. ambient temperature. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 ambient temperature (c) por trip voltage (v) downloaded from: http:///
MCP6V06/7/8 ds22093b-page 12 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. 2.3 frequency response figure 2-25: cmrr and psrr vs. frequency. figure 2-26: open-loop gain vs. frequency with v dd =1.8v. figure 2-27: open-loop gain vs. frequency with v dd =5.5v. figure 2-28: gain bandwidth product and phase margin vs. ambient temperature. figure 2-29: gain bandwidth product and phase margin vs. common mode input voltage. figure 2-30: gain bandwidth product and phase margin vs. output voltage. 0 10 20 30 40 50 60 70 80 90 100 110 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) cmrr, psrr (db) cmrr psrr+ psrr- 10 100k 1k 1m 10k 100 -30 -20 -10 0 10 20 30 40 50 60 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) open-loop gain (db) -270 -240 -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () | a ol | a ol 1k 10k 100k 1m 10m v dd = 1.8v c l = 60 pf -30 -20 -10 0 10 20 30 40 50 60 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) open-loop gain (db) -270 -240 -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () | a ol | a ol 1k 10k 100k 1m 10m v dd = 5.5v c l = 60 pf 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (mhz) 40 50 60 70 80 90 100 110 120 130 phase margin () v dd = 5.5v pm gbwp v dd = 1.8v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) gain bandwidth product (mhz) 40 50 60 70 80 90 100 110 120 130 phase margin () v dd = 5.5v pm v dd = 1.8v gbwp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) gain bandwidth product (mhz) 40 50 60 70 80 90 100 110 120 130 phase margin () v dd = 5.5 v pm v dd = 1.8v gbwp downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 13 MCP6V06/7/8 note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. figure 2-31: closed-loop output impedance vs. frequency with v dd =1.8v. figure 2-32: closed-loop output impedance vs. frequency with v dd =5.5v. figure 2-33: channel-to-channel separation vs. frequency. figure 2-34: maximum output voltage swing vs. frequency. 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) v dd = 1.8v 100k 1m 10m 100m 1 10 100 1k 10k g = 1 v/v g = 10 v/v g = 100 v/v open-loop output impedance ( ? ) 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) v dd = 5.5v 100k 1m 10m 100m 1 10 100 1k 10k g = 1 v/v g = 10 v/v g = 100 v/v open-loop output impedance ( ? ) 0 10 20 30 40 50 60 70 80 90 100 1.e+05 1.e+06 1.e+07 frequency (hz) channel-to-channel separation (db) v dd = 5.5v v dd = 1.8v rti 100k 1m 10m 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) maximum output voltage swing (v p-p ) v dd = 5.5v v dd = 1.8v 1k 10k 100k 1m downloaded from: http:///
MCP6V06/7/8 ds22093b-page 14 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. 2.4 input noise and distortion figure 2-35: input noise voltage density vs. frequency. figure 2-36: input noise voltage density vs. input common mode voltage. figure 2-37: inter-modulation distortion vs. frequency with v cm disturbance (see figure 1-7 ). figure 2-38: inter-modulation distortion vs. frequency with v dd disturbance (see figure 1-7 ). figure 2-39: input noise vs. time with 1 hz and 10 hz filters and v dd =1.8v. figure 2-40: input noise vs. time with 1 hz and 10 hz filters and v dd =5.5v. 10 100 1,000 10,000 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) 10 100 1000 input noise voltage; e ni (v p-p ) 10 1k 10k 100k e ni e ni (0 hz to f) input noise voltage density; e ni (nv/ hz) 100 v dd = 5.5v v dd = 1.8v 0 20 40 60 80 100 120 140 160 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) v dd = 5.5 v v dd = 1.8 v input noise voltage density; e ni (nv/ hz) 1 10 100 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) imd spectrum, rti (v pk ) g dm = 1 v/v v cm tone = 50 mv pk , f = 1 khz 100 1k 10k 100k imd tone at dc residual 1 khz tone v dd = 5.5v v dd = 1.8v 1 10 100 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) imd spectrum, rti (v pk ) 100 1k 10k 100k g dm = 1 v/v v dd tone = 50 mv pk , f = 1 khz imd tone at dc 1 khz tone v dd = 5.5v v dd = 1.8v 0 102030405060708090100 t (s) input noise voltage; e ni (t) (0.5 v/div) v dd = 1.8v npbw = 10 hz npbw = 1 hz 0 102030405060708090100 t (s) input noise voltage; e ni (t) (0.5 v/div) v dd = 5.5v npbw = 10 hz npbw = 1 hz downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 15 MCP6V06/7/8 note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. 2.5 time response figure 2-41: input offset voltage vs. time with temperature change. figure 2-42: input offset voltage vs. time at power up. figure 2-43: the MCP6V06/7/8 family shows no input phase reversal with overdrive. figure 2-44: non-inverting small signal step response. figure 2-45: non-inverting large signal step response. figure 2-46: inverting small signal step response. -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 0 20 40 60 80 100 120 140 160 180 200 time (s) input offset voltage (v) -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 pcb temperature (c) t pcb v os temperature increased by using heat gun for 4 seconds. -25 -20 -15 -10 -5 0 5 10 15 20 25 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 time (200 s/div) input offset voltage (mv) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 power supply voltage (v) por trip point v os v dd -1 0 1 2 3 4 5 6 7 012345678910 time (ms) input, output voltages (v) v dd = 5.5v g = 1 v out v in 02468101214161820 time (s) output voltage (10 mv/div) v dd = 5.5v g = 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 30 35 40 45 50 time (s) output voltage (v) v dd = 5.5v g = 1 012345678910 time (s) output voltage (10 mv/div) v dd = 5.5v g = -1 downloaded from: http:///
MCP6V06/7/8 ds22093b-page 16 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. figure 2-47: inverting large signal step response. figure 2-48: slew rate vs. ambient temperature. figure 2-49: output overdrive recovery vs. time with g = -100 v/v. figure 2-50: output overdrive recovery time vs. inverting gain. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 30 35 40 45 50 time (s) output voltage (v) v dd = 5.5v g = -1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) falling edge v dd = 5.5v v dd = 1.8v rising edge -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 time (50 s/div) output voltage (v) -1 0 1 2 3 4 5 6 input voltage g (v/v) v dd = 5.5v g = -100 v/v 0.5v overdrive v out g v in v out g v in 1 10 100 1000 1 10 100 1000 inverting gain magnitude (v/v) overdrive recovery time (s) 0.5v output overdrive t odr , low t odr , high v dd = 1.8v v dd = 5.5v downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 17 MCP6V06/7/8 note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. 2.6 chip select response (mcp6v08 only) figure 2-51: chip select current vs. power supply voltage. figure 2-52: power supply current vs. chip select voltage with v dd =1.8v. figure 2-53: power supply current vs. chip select voltage with v dd =5.5v. figure 2-54: chip select cu rrent vs. chip select voltage. figure 2-55: chip select voltage, output voltage vs. time with v dd =1.8v. figure 2-56: chip select voltage, output voltage vs. time with v dd =5.5v. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) chip select current (a) cs = v dd 0 50 100 150 200 250 300 350 400 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 chip select voltage (v) power supply current (a) v dd = 1.8v g = 1 v in = 0.9v v l = 0v hysteresis op amp turns on here op amp turns off here 0 100 200 300 400 500 600 0.00.51.01.52.02.53.03.54.04.55.05.5 chip select voltage (v) power supply current (a) v dd = 5.5v g = 1 v in = 2.75v v l = 0v hysteresis op amp turns on here op amp turns off here 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 chip select voltage (v) chip select current (a) v dd = 5.5v -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 time (5 s/div) output voltage (v) 0 1 2 3 4 5 6 7 8 9 10 11 12 chip select voltage (v) v dd = 1.8v g = +1 v/v v in = v dd r l = 10 k ? tied to v dd /2 cs v out on v out off v out off -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 30 35 40 45 50 time (5 s/div) output voltage (v) 0 3 6 9 12 15 18 21 24 27 30 33 36 39 chip select voltage (v) v dd = 5.5v g = +1 v/v v in = v dd r l = 10 k ? tied to v dd /2 cs v out on v out off v out off downloaded from: http:///
MCP6V06/7/8 ds22093b-page 18 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k to v l , c l = 60 pf, and cs = gnd. figure 2-57: chip select relative logic thresholds vs. ambient temperature. figure 2-58: chip select hysteresis. figure 2-59: chip select turn on time vs. ambient temperature. figure 2-60: chip selects pull-down resistor (r pd ) vs. ambient temperature. figure 2-61: quiescent current in shutdown vs. power supply voltage. 30% 35% 40% 45% 50% 55% 60% 65% 70% -50-25 0 255075100125 ambient temperature (c) relative chip select logic levels; low and high ( ) v il /v dd v ih /v dd v dd = 1.8v v dd = 5.5v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 ambient temperature (c) chip select hysteresis (v) v dd = 1.8v v dd = 5.5v 0 2 4 6 8 10 12 14 16 -50 -25 0 25 50 75 100 125 ambient temperature (c) chip select turn on time (s) v dd = 5.5v v dd = 1.8v 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 ambient temperature (c) pull-down resistor (m ? ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) power supply current (a) cs = v dd representative par t +125c +85c +25c -40c downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 19 MCP6V06/7/8 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 analog outputs the analog output pins (v out ) are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs (v in +, v in C, ) are high-impedance cmos inputs with low bias currents. 3.3 power supply pins the positive power supply (v dd ) is 1.8v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. 3.4 chip select (cs ) digital input this pin (cs ) is a cmos, schmitt-triggered input that places the mcp6v08 op amps into a low power mode of operation. 3.5 exposed thermal pad (ep) there is an internal connection between the exposed thermal pad (ep) and the v ss pin; they must be con- nected to the same potent ial on the printed circuit board (pcb). this pad can be connected to a pcb ground plane to provide a larger heat sink. this improves the package thermal resistance ( ja ). MCP6V06 mcp6v07 mcp6v08 symbol description tdfn soic dfn soic tdfn soic 661166v out , v outa output (op amp a) 222222v in C, v ina C inverting input (op amp a) 333333v in +, v ina + non-inverting input (op amp a) 444444 v ss negative power supply 5 5 v inb + non-inverting input (op amp b) 6 6 v inb C inverting input (op amp b) 7 7 v outb output (op amp b) 778877 v dd positive power supply 8 c s chip select (op amp a) 1, 5, 8 1, 5, 8 1, 5, 8 1, 5 nc no internal connection 9 9 9 ep exposed thermal pad (ep); must be connected to v ss downloaded from: http:///
MCP6V06/7/8 ds22093b-page 20 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 21 MCP6V06/7/8 4.0 applications the MCP6V06/7/8 family of auto-zeroed op amps is manufactured using microchi ps state of the art cmos process. it is designed for low cost, low power and high precision applications. its low supply voltage, low quiescent current and wide bandwidth makes the MCP6V06/7/8 ideal for battery-powered applications. 4.1 overview of auto-zeroing operation figure 4-1 shows a simplified diagram of the MCP6V06/7/8 auto-zeroed op amps. this will be used to explain how the dc voltage errors are reduced in this architecture. figure 4-1: simplified auto-zeroed op amp functional diagram. 4.1.1 building blocks the null amp. and main amp. are designed for high gain and accuracy using a differential topology. they have an auxiliary input (bottom left) used for correcting the offset voltages. both inputs are added together internally. the capacitors at the auxiliary inputs (c fw and c h ) hold the corrected values during normal operation. the output buffer is designed to drive external loads at the v out pin. it also produces a single ended output voltage (v ref is an internal reference voltage). all of these switches are make-before-break in order to minimize glitch-induced errors. they are driven by two clock phases ( 1 and 2 ) that select between normal mode and auto-zeroing mode. the clock is derived from an internal r-c oscillator running at a rate of f osc1 = 650 khz. the oscillators output is divided down to the desired rate. it is also randomized to minimize (spread) undesired clock tones in the output. the internal por ensures the part starts up in a known good state. it also provides protection against power supply brown out events. the chip select input places the op amp in a low power state when it is high. when it goes low, it powers the op amp at its normal level and starts operation properly. the digital control circuitry takes care of all of the housekeeping details of the switching operation. it also takes care of chip select and por events. v in + v in C main output v out v ref amp. buffer nc null amp. null input 1 switches null correct 2 switches null output switches c h c fw por digital control oscillator cs clock randomization 1 2 downloaded from: http:///
MCP6V06/7/8 ds22093b-page 22 ? 2008 microchip technology inc. 4.1.2 auto-zeroing action figure 4-2 shows the connections between amplifiers during the normal mode of operation ( 1 ). the hold capacitor (c h ) corrects the null ampl ifiers input offset. since the null amplifier has very high gain, it dominates the signal seen by the main amplifier. this greatly reduces the impact of the main amplifiers input offset voltage on overall pe rformance. essentially, the null amplifier and main amplifier behave as a regular op amp with very high gain (a ol ) and very low offset voltage (v os ). figure 4-2: normal mode of operation ( 1 ); equivalent amplifier diagram. figure 4-3 shows the connections between amplifiers during the auto-zeroing mode of operation ( 2 ). the signal goes directly through the main amplifier, and the flywheel capacitor (c fw ) maintains a constant correc- tion on the main amplifiers offset. the null amplifier uses its own high open loop gain to drive the voltage across c h to the point where its input offset voltage is almost zero. because the principal input is connected to v in +, the auto-zeroing action corrects the offset at the current common mode input voltage (v cm ) and supply voltage (v dd ). this makes the dc cmrr and psrr very high also. since these corrections happen every 50 s, or so, we also minimize slow errors, including offset drift with temperature ( v os / t a ), 1/f noise, and input offset aging. figure 4-3: auto-zeroing mode of operation ( 2 ); equivalent diagram. 4.1.3 intermodulat ion distortion (imd) the MCP6V06/7/8 op amps will show intermodulation distortion (imd), products when an ac signal is present. the signal and clock can be decomposed into sine wave tones (fourier series components). these tones interact with the auto-zeroing circuitrys non-linear response to produce imd tones at sum and difference frequencies. imd distortion tones are generated about all of the square wave clocks harmonics. see figure 2-37 and figure 2-38 . v in + v in C main output v out v ref amp. buffer nc null amp. c h c fw v in + v in C main output v out v ref amp. buffer nc null amp. c h c fw downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 23 MCP6V06/7/8 4.2 other functional blocks 4.2.1 rail-to-rail inputs the input stage of the MCP6V06/7/8 op amps uses two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm , which is approximately equal to v in + and v in C in nor- mal operation) and the other at high v cm . with this topology, the input operates with v cm up to 0.2v past either supply rail at +25c (see figure 2-18 ). the input offset voltage (v os ) is measured at v cm =v ss C0.2v and v dd + 0.2v to ensure proper operation. the transition between the input stages occurs when v cm v dd C 0.9v (see figure 2-7 and figure 2-8 ). for the best distortion and gain linearity, with non-inverting gains, avoid this region of operation. 4.2.1.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-43 shows an input voltage exceeding both supplies with no phase inversion. 4.2.1.2 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-4 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick esd events within the specified limits. figure 4-4: simplified analog input esd structures. in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see section 1.1 absolute maximum ratings ? ). figure 4-5 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in C) from going too far below ground, and the resistors r 1 and r 2 limit the possible current drawn out of the input pins. diodes d 1 and d 2 prevent the input pins (v in + and v in C) from going too far above v dd , and dump any currents onto v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-5: protecting the analog inputs. it is also possible to connect the diodes to the left of the resistor r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors th en serve as in-rush current limiters; the dc current into the input pins (v in + and v in C) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-17 . applications that are high impedance may need to limit the usable voltage range. 4.2.2 rail-to-rail output the output voltage range of the MCP6V06/7/8 auto-zeroed op amps is v dd C 15 mv (minimum) and v ss + 15 mv (maximum) when r l =20k is connected to v dd /2 and v dd = 5.5v. refer to figure 2-19 and figure 2-20 for more information. these op amps are designed to drive light loads; use another amplifier to buffer the output from heavy loads. 4.2.3 chip select (cs ) the single mcp6v08 has a chip select (cs ) pin. when cs is pulled high, the supply current for the corresponding op amp drops to about 1 a (typical), and is pulled through the cs pin to v ss . when this happens, the amplifier is put into a high impedance state. by pulling cs low, the amplifier is enabled. if the cs pin is left floating, the internal pull-down resistor (about 5 m ) will keep the part on. figure 1-4 shows the output voltage and supply current response to a cs pulse. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in C v 1 mcp6v0x r 1 v dd d 1 r 1 > v ss C (minimum expected v 1 ) 2ma v out r 2 > v ss C (minimum expected v 2 ) 2ma v 2 r 2 d 2 downloaded from: http:///
MCP6V06/7/8 ds22093b-page 24 ? 2008 microchip technology inc. 4.3 application tips 4.3.1 input offset voltage over temperature table 1-1 gives both the linear and quadratic tempera- ture coefficients (tc 1 and tc 2 ) of input offset voltage. the input offset voltage, at any temperature in the specified range, can be calculated as follows: equation 4-1: 4.3.2 dc gain plots figure 2-9 , figure 2-10 and figure 2-11 are histograms of the reciprocals (in units of v/v) of cmrr, psrr and a ol , respectively. they represent the change in input offset voltage (v os ) with a change in common mode input voltage (v cm ), power supply voltage (v dd ) and output voltage (v out ). the 1/a ol histogram is centered near 0 v/v because the measurements are do minated by the op amps input noise. the negative values shown represent noise, not unstable behavior. we validate the op amps stability by making multiple measurements of v os ; instability would manifest itself as a greater unex- plained variability in v os or as the railing of the output. 4.3.3 source resistances the input bias currents have two significant components; switching glitches that dominate at room temperature and below, and input esd diode leakage currents that dominate at +85c and above. make the resistances seen by the inputs small and equal. this minimizes the output offset caused by the input bias currents. the inputs should see a resistance on the order of 10 to 1 k at high frequencies (i.e., above 1 mhz). this helps minimize the impact of switching glitches, which are very fast, on overall perfo rmance. in some cases, it may be necessary to add re sistors in series with the inputs to achieve this improvement in performance. 4.3.4 source capacitance the capacitances seen by the two inputs should be small and matched. the internal switches connected to the inputs dump charges on these capacitors; an offset can be created if the ca pacitances do not match. 4.3.5 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loops phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. these auto-zeroed op amps have a different output impedance than most op amps, due to their unique topology. when driving a capacitive load with these op amps, a series resistor at the output (r iso in figure 4-6 ) improves the feedback loops phase margin (stability) by making the output load resistive at higher frequen- cies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-6: output resistor, r iso , stabilizes capacitive loads. figure 4-7 gives recommended r iso values for different capacitive loads and is independent of the gain. figure 4-7: recommended r iso values for capacitive loads. v os t a () v os tc 1 ttc 2 t 2 ++ = where: t=t a C25c v os (t a ) = input offset voltage at t a v os = input offset voltage at +25c tc 1 = linear temperature coefficient tc 2 = quadratic temperature coefficient r iso c l v out mcp6v0x 10 100 1000 10000 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 c l (f) recommended r iso ( ? ) 1p 10p 100p 1n 10n 100n 10 100 1k 10k g n < 2 g n = 5 g n = 10 downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 25 MCP6V06/7/8 after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify r iso 's value until the response is reasonable. bench evaluation and simulations with the MCP6V06 spice macro model (good for all of the mcp6v 06/7/8 op amps) are helpful. 4.3.6 stabilizing output loads this family of auto-zeroed op amps has an output impedance ( figure 2-31 and figure 2-32 ) that has a double zero when the gain is low. this can cause a large phase shift in feedback networks that have low resistance near the parts bandwidth. this large phase shift can cause stability problems. figure 4-8 shows one circuit example that has low resistance near the parts bandwidth. r f and c f set a pole at 0.16 khz, so the noise gain (g n ) is 1 v/v at the circuits bandwidth (roughly 1.3 mhz). the load seen by the op amps output at 1.3 mhz is r g ||r l (99 ). this is low enough to be a real concern. figure 4-8: output load issue. to solve this problem, increase the resistive load to at least 3 k . methods to accomplis h this task include: increase r g remove c f (relocate the filter) add a 3 k resistor at the op amps output that is not in the signal path; see figure 4-9 figure 4-9: one solution to output load issue. 4.3.7 reducing undesired noise and signals reduce undesired noise and signals with: low bandwidth signal filters: - minimizes random analog noise - reduces interfering signals good pcb layout techniques: - minimizes crosstalk - minimizes parasitic capacitances and induc- tances that interact with fast switching edges good power supply design: - isolation from other parts - filtering of interference on supply line(s) 4.3.8 supply bypassing and filtering with this family of operat ional amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm of the pin for good high-frequency performance. these parts also need a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other low noise, analog parts. additional filtering of high frequency power supply noise (e.g., switched mode power supplies) can be achieved using resistors. the resistors need to be small enough to prevent a large drop in v dd for the op amp, which would cause a reduced output range and possible load-induced power supply noise. the resis- tors also need to be large enough to dissipate little power when v dd is turned on and off quickly. the cir- cuit in figure 4-10 gives good rejection out to 1 mhz for switched mode power supplies. smaller resistors and capacitors are a better choice for designs where the power supply is reasonably quiet. figure 4-10: additional supply filtering. mcp6v0x c f 10.0 k r f 100 r g 100 r n v out v in 10.0 k r l 0.1 f mcp6v0x c f 10.0 k r f 100 r g 100 r n v out v in 10.0 k r l 0.1 f 3.01 k r x mcp6v0x v s_ana 143 143 100 f 100 f 0.1 f 1/4w 1/10w to other analog parts downloaded from: http:///
MCP6V06/7/8 ds22093b-page 26 ? 2008 microchip technology inc. 4.3.9 pcb design for dc precision in order to achieve dc precision on the order of 1 v, many physical errors need to be minimized. the design of the printed circuit board (pcb), the wiring, and the thermal environment has a strong impact on the precision achieved. a poor pcb design can easily be more than 100 times worse than the MCP6V06/7/8 op amps minimum and maximum specifications. 4.3.9.1 thermo-junctions any time two dissimilar metals are joined together, a temperature dependent vo ltage appears across the junction (the seebeck or thermo-junction effect). this effect is used in thermocouples to measure tempera- ture. the following are examples of thermo-junctions on a pcb: components (resistors, op amps, ) soldered to a copper pad wires mechanically attached to the pcb jumpers solder joints pcb vias typical thermo-junctions have temperature to voltage conversion coefficients of 10 to 100 v/c (sometimes higher). there are three basic approaches to minimizing thermo-junction effects: minimize thermal gradients cancel thermo-junction voltages minimize difference in thermal potential between metals 4.3.9.2 non-inverting and inverting amplifier layout for thermo-junctions figure 4-11 shows the recommended non-inverting and inverting gain amplifier circuits on one schematic. usually, to minimize the input bias current related off- set, r 1 is chosen to be r 2 ||r 3 . the guard traces (with ground vias at the ends) help minimize the thermal gradients. the resistor layout cancels the resistor thermal voltages, assuming the temperature gradient is c onstant near the resistors: equation 4-2: figure 4-11: pcb layout and schematic for single non-inverting and inverting amplifiers. note: changing the orientati on of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages. v out v p g p ,v m =gnd -v m g m ,v p =gnd where: g m =r 3 /r 2 , inverting gain magnitude g p =1+g m , non-inverting gain magnitude v os is neglected v p r 3 v out r 1 r 2 v m u 1 MCP6V06 u1 v m v out v p r3 r2r1 downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 27 MCP6V06/7/8 4.3.9.3 difference amplifier layout for thermo-junctions figure 4-12 shows the recommended difference ampli- fier circuit. usually, we choose r 1 =r 2 and r 3 =r 4 . the guard traces (with ground vias at the ends) help minimize the thermal gradients. the resistor layout cancels the resistor thermal voltages, assuming the temperature gradient is c onstant near the resistors: equation 4-3: figure 4-12: pcb layout and schematic for single difference amplifier. 4.3.9.4 dual non-invert ing amplifier layout for thermo-junctions the dual op amp amplifiers shown in figure 4-16 and figure 4-17 produce a non-inverting difference gain greater than 1, and a common mode gain of 1 .they can use the layout shown in figure 4-13 . the gain set- ting resistors (r 2 ) between the two sides are not com- bined so that the thermal voltages can be canceled. the guard traces (with ground vias at the ends) help minimize the thermal gradients. the resistor layout cancels the resistor thermal voltages, assuming the temperature gradient is c onstant near the resistors: equation 4-4: figure 4-13: pcb layout and schematic for dual non-inve rting amplifier. note: changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages. v out v ref +(v p Cv m )g dm where: thermal voltages are approximately equal g dm =r 3 /r 1 =r 4 /r 2 , difference gain v os is neglected v out v ref +(v p Cv m )g dm r 4 v out r 2 v m u 1 MCP6V06 v p r 1 r 3 v ref u1 v m v out v p r4 r2r1 r3 v ref note: changing the orientati on of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages. (v oa Cv ob ) (v ia Cv ib )g dm (v oa +v ob )/2 (v ia +v ib )/2 where: thermal voltages are approximately equal g dm =1+r 3 /r 2 , differential mode gain g cm = 1, common mode gain v os is neglected u1 v ib v oa v ob v ia r1 r2 r3 r1 r2 r3 v ib v ob r 1 u 1 ?mcp6v07 v ia r 3 v oa r 1 r 2 u 1 ?mcp6v07 r 3 r 2 downloaded from: http:///
MCP6V06/7/8 ds22093b-page 28 ? 2008 microchip technology inc. 4.3.9.5 other pcb thermal design tips in cases where an individual resistor needs to have its thermo-junction voltage cancelled, it can be split into two equal resistors as shown in figure 4-14 . to keep the thermal gradients near the resistors as small as possible, the layouts are symmetrical with a ring of metal around the outside. make r 1a =r 1b =r 1 /2 and r 2a =r 2b =2r 2 . figure 4-14: pcb layout for individual resistors. minimize temperature gradients at critical components (resistors, op amps, heat sources, etc.): minimize exposure to gradients - small components - tight spacing - shield from air currents align with constant temperature (contour) lines - place on pcb center line minimize magnitude of gradients - select parts with lower power dissipation - use same metal junctions on thermo-junc- tions that need to match - use metal junctions with low temperature to voltage coefficients - large distance from heat sources - ground plane underneath (large area) - fr4 gaps (no copper for thermal insulation) - series resistors inserted into traces (adds thermal and electrical resistance) - use heat sinks make the temperature gradient point in one direction: add guard traces - constant temperature curves follow the traces - connect to ground plane shape any fr4 gaps - constant temperature curves follow the edges 4.3.9.6 crosstalk dc crosstalk causes offsets that appear as a larger input offset voltage. common causes include: common mode noise (remote sensors) ground loops (current return paths) power supply coupling interference from the mains (usually 50 hz or 60 hz), and other ac sources, can also affect the dc perfor- mance. non-linear distortion can convert these signals to multiple tones, included a dc shift in voltage. when the signal is sampled by an adc, these ac signals can also be aliased to dc, causing an apparent shift in offset. to reduce interference: - keep traces and wires as short as possible - use shielding (e.g., encapsulant) - use ground plane (at least a star ground) - place the input signal source near to the dut - use good pcb layout techniques - use a separate power supply filter (bypass capacitors) for these auto-zeroed op amps 4.3.9.7 miscellaneous effects keep the resistances seen by the input pins as small and as near to equal as possible to minimize bias cur- rent related offsets. make the (trace) capacitances seen by the input pins small and equal. this is helpful in minimizing switching glitch-induced offset voltages. bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center or (the tribo-electric effect). make sure the bending radius is large enough to keep the conductors and insulation in full contact. mechanical stresses can make some capacitor types (such as ceramic) to out put small voltages. use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. humidity can cause electro- chemical potential voltages to appear in a circuit. proper pcb cleaning helps, as does the use of encapsulants. note: changing the orientation of the resistors will usually cause a significant decrease in the cancellation of the thermal voltages. r 1b r 1a r 2b r 2a r 1b r 1a r 2b r 2a downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 29 MCP6V06/7/8 4.4 typical applications 4.4.1 wheatstone bridge many sensors are configured as wheatstone bridges. strain gauges and pressure sensors are two common examples. these signals can be small and the common mode noise large. amplifier designs with high differential gain are desirable. figure 4-15 shows how to interface to a wheatstone bridge with a minimum of components. because the circuit is not symmetric, t he adc input is single ended, and there is a minimum of filtering, the cmrr is good enough for moderate common mode noise. figure 4-15: simple design. figure 4-16 shows a higher performance circuit for wheatstone bridges. this circuit is symmetric and has high cmrr. using a differential input to the adc helps with the cmrr. figure 4-16: high performance design. 4.4.2 rtd sensor the ratiometric circuit in figure 4-17 conditions a three wire rtd. it corrects for the sensors wiring resistance by subtracting the voltage across the middle r w . the top r1 does not change the output voltage; it balances the op amp inputs. failure (open) of the rtd is detected by an out-of-range voltage. figure 4-17: rtd sensor. the voltages at the input of the adc can be calculated with the following: v dd rr rr 100r 0.01c MCP6V06 adc v dd 0.2r 0.2r 3k 20 k 1f 200 20 k 1f adc v dd ? mcp6v07 ? mcp6v07 200 200 3k 3k 1f rr rr v dd 10 nf 10 nf 200 r 3 100 nf 10 nf r 2 r 3 100 nf adc v dd ? mcp6v07? mcp6v07 2.49 k 2.49 k 10 nf v dd r w r w r w r t r b r rtd r 1 r 1 1f 100 3k 3k 20 k 20 k 100 k 100 k 2.49 k 2.49 k r 2 2.55 k 2.55 k v dm g rtd v t v b C () g w v w + = v cm v t v b g rtd 1g w C + () v w ++ 2 ------------------------------------------------------------------------------ = g rtd 12r 3 r 2 ? ? + = g w g rtd r 3 r 1 ? C = where: v t = voltage at the top of r rtd v b = voltage at the bottom of r rtd v w = voltage across top and middle r w s v cm = adcs common mode input v dm = adcs differential mode input downloaded from: http:///
MCP6V06/7/8 ds22093b-page 30 ? 2008 microchip technology inc. 4.4.3 thermocouple sensor figure 4-18 shows a simplified diagram of an amplifier and temperature sensor used in a thermocouple application. the type k thermocouple senses the temperature at t he hot junction (t hj ), and produces a voltage at v 1 proportional to t hj (in c). the amplifiers gain is is set so that v 4 /t hj is 10 mv/c. v 3 represents the output of a temperatur e sensor, which produces a voltage proportional to the temperature (in c) at the cold junction (t cj ), and with a 0.50v offset. v 2 is set so that v 4 is 0.50v when t hj Ct cj is 0c. equation 4-5: figure 4-18: thermocouple sensor; simplified circuit. figure 4-19 shows a more complete implementation of this circuit. the dashed red arrow indicates a thermally conductive connection between the thermocouple and the mcp9700a; it needs to be very short and have low thermal resistance. figure 4-19: thermocouple sensor. the mcp9700a senses the temperature at its physical location. it needs to be at t he same temperature as the cold junction (t cj ), and produces v 3 ( figure 4-16 ). the mcp1541 produces a 4.10v output, assuming v dd is at 5.0v. this voltage, tied to a resistor ladder of 4.100(r th ) and 1.3224(r th ), would produce a theve- nin equivalent of 1.00v and 250(r th ). the 1.3224(r th ) resistor is combined in parallel with the top right r th resistor (in figure 4-18 ), producing the 0.5696(r th ) resistor. v 4 should be converted to digital, then corrected for the thermocouples non-linearity. the adc can use the mcp1541 as its voltage reference. alternately, an absolute reference inside a picmicro ? can be used instead of the mcp1541. 4.4.4 offset voltage correction figure 4-20 shows a MCP6V06 correcting the input offset voltage of another op amp. r 2 and c 2 integrate the offset error seen at the other op amps input; the integration needs to be slow enough to be stable (with the feedback provided by r 1 and r 3 ). figure 4-20: offset correction. 4.4.5 precision comparator use high gain before a comparator to improve the latters performance. do not use MCP6V06/7/8 as a comparator by itself; the v os correction circuitry does not operate properly without a feedback loop. figure 4-21: precision comparator. v 1 t hj (40 v/c) v 2 = (1.00v) v 3 =t cj (10 mv/c) + (0.50v) v 4 =250v 1 +(v 2 Cv 3 ) (10 mv/c) (t hj Ct cj ) + (0.50v) (r th )/250 (r th ) (r th )/250 c (r th ) c v 4 MCP6V06 type k 40 v/c (r th ) (r th ) v 1 v 3 (hot junction (cold junction v 2 thermocouple at t hj ) at t cj ) r th = thevenin equivalent resistance (r th )/250 0.5696(r th ) (r th )/250 c (r th ) c v 4 MCP6V06 type k (r th ) 4.100(r th ) v 1 mcp9700a v dd mcp1541 v dd 3k r th = thevenin equivalent resistance (e.g., 10 k ) MCP6V06 c 2 r 2 r 1 r 3 mcp6xxx v dd /2 3k v in v out r 2 MCP6V06 v in r 3 r 2 v dd /2 mcp6541 v out r 5 r 4 r 1 1k downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 31 MCP6V06/7/8 5.0 design aids microchip provides the basic design aids needed for the MCP6V06/7/8 family of op amps. 5.1 spice macro model the latest spice macro model for the MCP6V06/7/8 op amps is available on the microchip web site at www.microchip.com. this model is intended to be an initial design tool that works well in the op amps linear region of operation over t he temperature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchips filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the micro- chip web site at www.microc hip.com/filterlab, the fil- ter-lab design tool provides full schematic diagrams of the filter circuit with compon ent values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter perfor- mance. 5.3 mindi? circuit designer & simulator microchips mindi? circuit designer & simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. it is a free online circuit designer & simulator available from the microchip web site at www.microchip.com/mindi. this interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, and simulate circuits. circuits developed using the mindi circuit designer & simulator can be downloaded to a personal computer or workstation. 5.4 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design require- ment. available at no cost from the microchip website at www.microchip.com/maps, the maps is an overall selection tool for microchips product portfolio that includes analog, memory, mcus and dscs. using this tool, a customer can define a filter to sort features for a parametric search of devi ces and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.5 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demon- stration and evaluation boar ds that are designed to help customers achieve faster time to market. for a complete listing of these boards and their correspond- ing users guides and technical information, visit the microchip web site at www.microchip.com/analog tools. some boards that are especially useful are: mcp6v01 thermocouple auto-zeroed reference design mcp6xxx amplifier evaluation board 1 mcp6xxx amplifier evaluation board 2 mcp6xxx amplifier evaluation board 3 mcp6xxx amplifier evaluation board 4 active filter demo board kit p/n soic8ev: 8-pin soic/msop/tssop/dip evaluation board p/n soic14ev: 14- pin soic/tssop/dip evaluation board 5.6 application notes the following microchip application notes are available on the microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. adn003: select the right operational amplifier for your filtering circuits , ds21821 an722: operational amplifier topologies and dc specifications , ds00722 an723: operational amplifier ac specifications and applications , ds00723 an884: driving capacitive loads with op amps , ds00884 an990: analog sensor conditioning circuits C an overview , ds00990 these application notes and others are listed in the design guide: signal chain design guide, ds21825 downloaded from: http:///
MCP6V06/7/8 ds22093b-page 32 ? 2008 microchip technology inc. 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead soic (150 mil) example : xxxxxxxxxxxxyyww nnn mcp6vo6 e sn 0823 256 3 e xxxxxx 8-lead dfn (4x4) (mcp6v07) xxxxxx yyww nnn example 6v07 e/md^^ 0823 256 3 e 8-lead tdfn (2x3) (MCP6V06, mcp6v08) example: xxxyww nn aac838 25 device code MCP6V06 aac mcp6v08 aad note: applies to 8-lead 2x3 tdfn downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 33 MCP6V06/7/8

!"#$ %

! "#$%& '$ (#)* ( ! +

,%-* ,!

% -
$# *... / $0110$%+%,# ! 1 $02 23$ $"4 2
2 5 656(#) 37 " 656 686 66 # " 666 66 66' )+ " 66,%- 31 ! 66(#) % 9 % 666 6 56 39 % 66(#) % 1 ! 666 66 :6 )9 6' 66 6' )1 1 66 6'' 6:' );;% < 66 = = d n e note 1 1 2 a3 a a1 note 2 note 1 d2 1 2 e2 l n e b k exposed pad top view bottom view $ + ! )6 ;) downloaded from: http:///
MCP6V06/7/8 ds22093b-page 34 ? 2008 microchip technology inc.
&
'
(&))*+ !"#&',-$ %

>#) ! ! %

$
6' ! "#$%& '$ (#)* ( ! +

,%-* ,!

% -
$# *... / $0110$%+%,# ! 1 $02 23$ $"4 2
2 5 ?(#) 37 " = = ?' $ + " ' = = # > " 66 = 6' 39 % :66(#) $ 9 % 86(#) 31 ! 86(#) )@a 6' = 6'6 -1 1 6 6 = ? - 1 6 ,%- -" 6b = 5b 1 + 6? = 6' 1 9 6 = 6' $ !"+ 'b = 'b $ !"( 'b = 'b d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h $ + ! )6 ;6'?( downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 35 MCP6V06/7/8
&
'
(&))*+ !"#&',-$ % -
$# *... downloaded from: http:///
MCP6V06/7/8 ds22093b-page 36 ? 2008 microchip technology inc.

.+/0 !"#1$ % -
$# *... downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 37 MCP6V06/7/8

.+/0 !"#1$ % -
$# *... downloaded from: http:///
MCP6V06/7/8 ds22093b-page 38 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 39 MCP6V06/7/8 appendix a: revision history revision b (december 2008) the following is the list of modifications: 1. added the 8-lead, 2x3 tdfn package for the mcp6v01 and mcp6v03 devices. 2. added 8-lead, 2x3 tdfn package information to thermal characteristic table. 3. added information on the exposed thermal pad (ep) for the 8-lead, 2x3 tdfn and 8-lead, 4x4 dfn packages. 4. added section 4.3.6 stabilizing output loads . 5. other minor typographical corrections. revision a (june 2008) original release of this document. downloaded from: http:///
MCP6V06/7/8 ds22093b-page 40 ? 2008 microchip technology inc. appendix b: offset related test screens input offset voltage related specifications in the dc spec table ( table 1-1 ) are based on bench measure- ments (see section 2.1 dc input precision ). these measurements are much more accurate because: more compact circuit soldered parts on the pcb more time spent averaging (reduces noise) better temperature control - reduced temperature gradients - greater accuracy we use production screens to ensure the quality of our outgoing products. these screens are set at wider lim- its to eliminate any fliers; see ta b l e b - 1 . table b-1: offset related test screens electrical characteristics: unless otherwise indicated, t a = 25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2, r l = 20 k to v l , and cs = gnd (refer to figure 1-5 and figure 1-6 ). parameters sym min max units conditions input offset input offset voltage v os -10 +10 v t a = +25c (note 1, note 2) input offset voltage drift with temperature (linear temp. co.) tc 1 n v / ct a = -40 to +125c (note 3) power supply rejection psrr 115 db (note 1) common mode common mode rejection cmrr 106 db v dd = 1.8v, v cm = -0.2v to 2.0v (note 1) cmrr 116 db v dd = 5.5v, v cm = -0.2v to 5.7v (note 1) open-loop gain dc open-loop gain (large signal) a ol 114 db v dd = 1.8v, v out = 0.2v to 1.6v (note 1) a ol 122 db v dd = 5.5v, v out = 0.2v to 5.3v (note 1) note 1: due to thermal junctions and other errors in the produc tion environment, these specific ations are only screened in production. 2: v os is also sample screened at +125c. 3: tc 1 is not measured in production. downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 41 MCP6V06/7/8 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: MCP6V06 single op amp MCP6V06t single op amp (tape and reel for 2x3 tdfn and soic) mcp6v07 dual op amp mcp6v07t dual op amp (tape and reel for 44 dfn and soic) mcp6v08 single op amp with chip select mcp6v08t single op amp with chip select (tape and reel for soic) temperature range: e = -40c to +125c package: md = plastic dual flat, no-lead (44x0.9 mm), 8-lead (mcp6v07 only) mny * = plastic dual flat, no-lead (23x0.75 mm), 8-lead (MCP6V06, mcp6v08) sn = plastic soic (150mil body), 8-lead * y = nickel palladium gold manufacturing designator. only available on the tdfn package. part no. Cx /xx x package temperature range device examples: a) MCP6V06t-e/sn: extended temperature, 8ld soic package. b) MCP6V06-e/mny: extended temperature, 8ld 2x3 tdfn package. a) mcp6v07-e/md: extended temperature, 8ld 4x4 dfn package.. b) mcp6v07t-e/sn: tape and reel, extended temperature, 8ld soic package. a) mcp6v08-e/sn: extended temperature, 8ld soic package. b) mcp6v08-e/mny:extended temperature, 8ld 2x3 tdfn package. downloaded from: http:///
MCP6V06/7/8 ds22093b-page 42 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22093b-page 43 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic, smartshunt and uni/o are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
ds22093b-page 44 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 downloaded from: http:///

▲Up To Search▲

Price & Availability of MCP6V06

	To Download MCP6V06 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .